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74F109 Specifications

Detailed technical information and Application Scenarios

Product Details

PartNumberManufactorQuantityAvailability
74F109NS273Yes

74F109** is a dual positive-edge-triggered J-K flip-flop with set and reset, manufactured by **National Semiconductor (NS)**.

The 74F109 is a dual positive-edge-triggered J-K flip-flop with set and reset, manufactured by National Semiconductor (NS).

Key Specifications:

  • Logic Family: 74F (Fast TTL)
  • Function: Dual J-K Flip-Flop with Set and Reset
  • Trigger Type: Positive-edge-triggered
  • Operating Voltage: 5V ±10%
  • Propagation Delay: Typically 5.5 ns (max 9 ns)
  • Output Drive Capability: Standard TTL (fan-out of 10)
  • Operating Temperature Range: 0°C to +70°C (commercial)
  • Package Options: 16-pin DIP, SOIC, or other surface-mount packages

Features:

  • Independent J-K inputs for each flip-flop
  • Asynchronous Set (PRE) and Clear (CLR) inputs
  • High-speed operation (compatible with 74F series)
  • Direct interface with TTL, CMOS, and other logic families
  • Low power consumption compared to standard TTL

Pin Configuration (Dual Flip-Flop):

  • Flip-Flop 1: Clock (1CP), J (1J), K (1K), Set (1PRE), Reset (1CLR), Q (1Q), Q̅ (1Q̅)
  • Flip-Flop 2: Clock (2CP), J (2J), K (2K), Set (2PRE), Reset (2CLR), Q (2Q), Q̅ (2Q̅)
  • VCC (Pin 16), GND (Pin 8)

Applications:

  • Counters and registers
  • State machine control
  • Data synchronization
  • General-purpose digital logic circuits

This information is based on the original National Semiconductor datasheet for the 74F109. For exact timing diagrams and electrical characteristics, refer to the official documentation.

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